This invention is used in microprogram-controlled processors in which the operation code of the macroinstructions serves to address a control storage storing both an operation code table and the microinstructions which are required for executing the macroinstructions. The operation code of the macroinstruction is generally converted by the operation code table into an address which also refers to the control storage and at which the control storage contains the first microinstruction of a micro routine which is used to execute the respective macroinstruction.
The microinstructions read from the control storage, which are generally referred to as control words, are fed to a microinstruction operation register where they are buffered and from where they are fed to an instruction decoder linking the control words with the instruction cycle times, thus generating cycle time related control signals which subsequently control the data flow control elements, such as set inputs of registers, gate circuits, and the like. The sequential address of the respective next microinstruction of a routine can be generated in various ways. One way for example is by modifying the address of the control storage address register in a +1 modifier. Another way is by simply including it in the microinstructions proper.
In the earlier period of computer development, the control unit, also known as the instruction unit, generally contained permanently wired circuit logic. This had the following disadvantages: the structure of the logic was poorly organized and difficult to change; and the logic circuit costs were too high. Early attempts at improving the control units of processors led to a systematic storage-oriented structure of the control logic which was referred to as microprogramming and microprogram control, respectively. From the logic standpoint, a microprogram routine is a subroutine for executing a machine or macroinstruction.
At this time, the microprogram was written into read-only storages, whose outputs on the hardware level performed fixed control functions. The output lines were, for example, set lines for registers, or lines for gate control signals. A bit in a microinstruction indicated that the line for that microinstruction was to be activated. The structure of such a microinstruction was referred to as horizontal on account of its length of 100 bits or more.
The chief disadvantage of this approach is the poor utilization of the microprogram storage. The largest part of the storage capacity is not utilized since individual control signals are not required for each micro or control word. The relevant storage bits, since they are uncoded, do not contain information. Another problem arises when using a microinstruction with a vertical format. This format very much resembles that of a normal macroinstruction. The function of the instruction is contained in the operation code in a highly coded format. The remainder of the instruction substantially consists of address fields, because a microinstruction with a vertical format, unlike a microinstruction with a horizontal format, also permits addressing internal address registers. The microinstruction is more complex since its functional content corresponds to that of several otherwise serially executed horizontal instructions. This highly complex function has to be subdivided into appropriate individual steps, which in computers produced so far was generally done by a circuit-wired control logic.
In using such circuit-wired control logic, the microinstruction is merely used to invoke a hardware sequence control which decodes the operation code as well as other information, and converts the same into a sequence of elementary steps. This hierarchical structure leads to multiple use of the sequence control. The vertical format control storage can be slower since execution of the instructions takes longer because of the interconnected control logic. A strictly vertical format has the disadvantage that the control processes are heavily serialized, which adversely affects the processing speed of a processor as a whole.
A microinstruction with coded instruction fields, whose format can be referred to as quasi-horizontal, strikes a compromise between horizontal and vertical formats. The total operation code is divided into subfunctions which are rigidly linked with individual bit groups of the format. In addition, it is possible to insert direct control bits and similar function elements. A single instruction of this type causes more functions to be executed in parallel than an instruction with a vertical format, so that the instruction length may again reach 50 bits or more. Compared with the vertical format, decoding is simpler and faster.
A combination of a directly hardware-controlled machine and an interpretatively, i.e., microprogram-controlled, machine is well known. To increase the processing speed of microprogram-controlled processors, without at the same time considerably increasing the number of circuits used, the macro and microinstructions have the same format. This permits a circuit design for the instruction control unit which is such that simple macroinstructions for performing simple functions, such as "load register", "store register in main storage", and the like, can be directly executed. More complex macroinstructions, such as floating point operations or decimal arithmetic functions, are interpretatively executed, but by means of microinstructions which are also directly executable, using the same circuits. The directly executable microinstructions are identical with the previously mentioned directly executable simple macroinstructions which also occur directly in the user program.
Thus, a user program consists of a sequence of simple and complex macro instructions. For instruction execution, it is determined in advance by testing the operation code whether the instruction to be currently processed is one which can be directly executed or one which has to be interpreted by other directly executable instructions. As a function of the test result, a switch is set, switching the instruction control unit either to the micro or the macro mode. For more complex macroinstructions, a branch is taken to an interpretation unit which is a normal micro program control with a control storage and an instruction sequence control. Since all macroinstructions can now be executed by the instruction execution hardware, the more complex macroinstructions, similar to the simple macroinstructions, are transferred from the interpretation unit to the instruction execution unit.
The chief disadvantage of such an arrangement is that the design and flexibility of the processor architecture and the instruction set are restricted, since extreme care must be taken that the simple macroinstructions suit the more complex macroinstructions and vice versa. In addition, processing time is lost by testing the operation code for complex or simple macro instructions.
Accordingly it is an object of this invention to provide an improved microprogram-controlled processor.
It is another object of this invention to provide for the direct hardware controlled execution of instructions in a microprogram-controlled processor.
It is a further object of this invention to provide a control unit for a microprogram-controlled processor which is flexible with regard to the design of the instruction sets and which has a high processing speed and reduced circuit requirements with respect to the instruction decoder.